This invention is directed generally to digital systems, and in particular to a semiconductor memory system in the form of a wafer scale integrated array of substantially identically formed memory-containing cells.
Digital systems of virtually every type use some form of secondary memory (primary memory being typically random access memory that form main, cache, and other memory from which operating systems and applications programs are run). Preferred secondary memory would be semiconductor of one form or another due to such advantages as speed of operation and small size. But, due the fact that the quantity of data to be stored is often very large, that it be retained for long periods of time, and with some permanence (i.e., be impervious to power loss/outages), other forms of secondary storage are used. Often these other forms of secondary storage are of the type using magnetic media (e.g., disk or tape). The principal differences between the primary and secondary storage are two: access speed and capacity. Thus, secondary storage often provides the advantage of very high storage capacity, accompanied by the relative disadvantage of undesirable access times. This is among the reasons, as will be evident to those of ordinary skill in this art, that such schemes as virtual memory have been implemented to take advantage of the high storage capacity offered by secondary storage, while masking the relatively slow data access speeds encountered.
There have been attempts to construct secondary storage systems using solid state, semiconductor memory devices by placing more and more memory circuitry onto each chip, thereby increasing circuit size and complexity. However, as circuit size increases, the chances of flaws forming in the circuit also increases, tending to reduce the yield of useable chips from a wafer. Yet other approaches propose mechanically interconnecting integrated circuit memory devices to construct a large scale memory system. However, the necessary chip-to-chip connections in such systems which tend to reduce circuit speed, introduce noise, and give rise to reliability problems caused by mechanical failure. Also, driver circuits are often needed to provide the necessary drive current for signals that are brought off-chip, at the expense of circuit area. There are also economic considerations: Memory systems developed from multiple chips, in addition to being labor intensive, are subject to higher packaging and manufacturing costs than if implemented in fewer (or, ideally, one) chips. Thus, these latter approaches, albeit successful to an extent, are accompanied by problems that make them attractive mostly when other available forms of secondary storage (i.e., disk systems) are, for whatever reason, not acceptable for the particular application. In sum, all these, and other, reasons combine to make the prospect of a memory system capable of being formed on an entire semiconductor wafer very attractive.
Since commercial introduction of integrated circuitry, there has been a continuing trend toward putting more and more circuitry onto smaller and smaller areas of integrated circuit chips. It is not too surprising, therefore, to see that very large scale integration (VLSI) techniques are giving way to wafer scale integration as a response to the increasing demand for higher integrated circuit density. Wafer scale integration provides a large density advantage over VLSI.
Wafer scale integration seeks to assemble an entire system on a single wafer, rather than partition the wafer into chips that each carry smaller portions of a system, and thereby requires the expense of individual packaging. However, yield has been one problem that works against successful wafer scale integration. Fabrication flaws must be overcome in order to effectively and economically use wafer scale integration techniques.
There are a number of wafer scale techniques known today aimed at overcoming the yield problem. One such technique utilizes redundant copies of a digital system formed on a wafer, and provides selection circuitry integrated in each of the systems. The selection circuitry intercouples portions of each copy of the system in a manner that results in one, flaw-free, working version of the desired digital system. An example of this technique can be seen in U.S. Pat. No. 4,621,201. Other approaches can be found in W. R. Moore, "A Review of Fault Tolerant Techniques for the Enhancement of Integrated Circuit Yield," Proc. of the IEEE, Vol. 74, May, 1986, pp. 684-698; W. Chen, et al., "A WSI Approach Towards Defect/Fault Tolerant Reconfigurable Serial Systems," IEEE Journal of Solid State Circuits, Vol. 23, June, 1988, pp. 639-646; J. Trilhe and G. Saucier, "WSI--The Challenge of the Future"; Proc. IEEE Conference on VLSI and Computers, May, 1987. These interconnecting techniques can tend to use more wafer area, create more complex circuitry, and pose a routing problem for signal lines.
Yet another, more simplified approach, is to have bi-directional busses connecting each rectangular cell to its four adjacent neighbors. The input to the cell is selected from one of the four neighbors, and the output driven to a different neighbor. The main problem with such a structure is that every cell must have two operating neighbor cells in order to be included in a linear array or "chain" of such cells. Also, it is difficult to configure a chain in such a way that both the beginning and end are on a wafer periphery where they may be connected to bonding pads.
A more practical cell interconnection approach has been to provide separate inputs and outputs between a cell and each of its neighbors to increase interconnection flexibility. In this approach, the cell carries a logic function whose input may be selected from any one of the four neighbors, and whose output is, in turn, communicated to the selection logic associated with each boundary (which also receives inputs from each of the other boundaries). Although this structure provides sufficient paths to connect around many defective cells, there are several drawbacks: The delay between the logic functions of any two cells depends upon the number of individual selection logic elements between them. Since this is not known at the outset, the delay is unbounded. Also, the amount of logic to implement the selection logic (e.g., multiplexers) may take up a significant area of the cell, and particularly so when the information is communicated in parallel instead of bit serial form. Further, the routing of the necessary signal lines tends to be irregular and confused; since every side must connect to every other side, it is possible that interference with logic routing lines will be encountered. Further still, it is difficult to find an acceptable configuration algorithm that allows connection to any reachable cell. This and similar structures are discussed in T. Leighton and C. E. Leiserson, "Algorithms for Integrating Wafer Scale Systolic Arrays," Systolic Signal Processing Systems, Dekker, 1987, pp. 299-326; M. J. Shute and P. E. Osman, "COBWEB--A Reduction Architecture," Wafer Scale Integration; Adam Hilger, 1986, pp. 169-178; and M. G. H. Katevenis and M. G. Blatt, "Switch Design for Soft-Configurable WSI Systems"; Proc. IFIP Int'l Workshop on WSI, Elsevier Science Publishers, 1986, pp. 255-270.
A modification of the foregoing approach is implemented in a wafer-scale integrated memory system. Each cell carries a pair of shift registers that are used, when connected to neighbor cells, to form a spiral, consisting of a single, long shift register chain. The first half of the path through the shift register chain is formed by one of the shift registers of each cell; the return path contains the second shift register of each cell. There are two inputs to the cell from each neighbor cell; one input (from each neighbor) is multiplexed to the input of one of the shift registers, the other input (from each boundary) to the other shift register. In similar fashion the outputs of each shift register are multiplexed to one of two outputs to each neighbor. While this scheme may simplify the multiplex circuitry used in the connection techniques discussed above, it still requires more than is believed needed. Further, known implementations of the approach use a cell-to-cell connection scheme that lacks flexibility, resulting, it is believed, in a less than optimum harvest of those cells available for inclusion in the chain. (As used herein, "harvest" is used to refer to those cells that are actually included in any interconnection of the cells, relative to the number of cells on the wafer that operable.) An example of this approach is found in U.S. Pat. No. 3,913,072.
There have been also approaches that have amplified the aforementioned basic structure, adding connections to additional neighbors (hexagonal arrays--see M.J. Shute, supra) or neighbors that are not edge-adjacent (i.e., corner neighbors). These designs, however, tend to suffer from the same general problems as the rectangular approach, both offer some increased harvest at the expense of extra cell area and layout difficulties.